Computerized devices control almost every aspect of our life—from writing documents to controlling traffic lights. However, computerized devices are bug-prone, and thus require a testing phase in which the bugs should be discovered. The testing phase is considered one of the most difficult tasks in designing a computerized device. The cost of not discovering a bug may be enormous, as the consequences of the bug may be disastrous. For example, a bug may cause the injury of a person relying on the designated behavior of the computerized device. Additionally, a bug in hardware or firmware may be expensive to fix, as patching it requires call-back of the computerized device. Hence, many developers of computerized devices invest a substantial portion of the development cycle to discover erroneous behaviors of the computerized device.
Functional verification is one method that may be employed to increase quality of the computerized device. Functional verification aims at checking that the design of the computerized device is in accordance with requirements. One method of performing functional verification is by generating stimuli and injecting the stimuli to the target system or a simulation thereof. The target system is also referred to as a Design Under Test (DUT). The generation may be biased towards stimuli of relatively high quality. Generation may be based on one or more generation streams. The streams may be manually defined, may be generated based on test templates, or the like.
The generated stimuli may be provided to DUT or a simulation thereof. The simulation may be performed by a simulator, an emulator, a post-silicon product of the target system, a prototype of the target system, or the like It will be noted that simulation of the DUT may be performed by a device, such as a simulator, capable of simulating execution of the DUT based on a descriptive language describing the DUT, such as for example an Hardware Descriptive Language (HDL), SystemC, Verilog or the like. In some exemplary embodiments, online generators employ generation-simulation cycles, in which one or more operations that stimulate the DUT are generated and are provided to the DUT or simulation thereof. Additionally or alternatively, offline generators may generate the operations and once all operations are generated, utilize them to stimulate the DUT or simulation thereof.